56 Gb/s PAM-4 Optical Receiver Frontend in an Advanced FinFET Process
Additional Document Info
2015 IEEE. This paper presents a 56Gb/s PAM-4 optical receiver analog frontend circuits which consists of three inverter stages TIA with resistive feedback in the first and third stages. An adaptively-tuned continuous-time linear equalizer (CTLE) is cascaded after the TIA for improved sensitivity and bandwidth. The overall gain is controlled by an automatic gain control (AGC) circuits to avoid the large input optical power saturates the TIA, thus distorting the PAM-4 signals. The frontend receiver circuits is designed in an advanced FinFET technology and overall gain achieves 68 dBO with a 22 GHz bandwidth. The simulated input referred current rms noise is 2.86 A. Total chip power is 6.3 mW from a 0.83 V supply. The chip active area is 150m 100 m.
name of conference
2015 IEEE 58th International Midwest Symposium on Circuits and Systems (MWSCAS)