A 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65nm CMOS Conference Paper uri icon


  • 2016 IEEE. A dual-mode NRZ/PAM4 SerDes seamlessly supports both modulations with a 1-FIR- and 2-IIR-tap DFE receiver and a 4/2-tap FFE transmitter in NRZ/PAM4 modes, respectively. A source-series-terminated (SST) transmitter employs lookup-table (LUT) control of a 31-segment output DAC to implement FFE equalization in NRZ and PAM4 modes with 1.2Vpp output swing and utilizes low-overhead analog impedance control. Optimization of the quarter-rate transmitter serializer is achieved with a tri-state inverterbased mux with dynamic pre-driver gates. The quarter-rate DFE receiver achieves efficient equalization with 1-FIR tap for the large first post-cursor ISI and 2-IIR taps for long-tail ISI cancellation. Fabricated in GP 65-nm CMOS, the transceiver occupies 0.074 mm2 area and achieves power efficiencies of 10.9 and 5.5 mW/Gbps with 16Gb/s NRZ and 32Gb/s PAM4 data, respectively.

name of conference

  • 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

published proceedings

  • 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

author list (cited authors)

  • Roshan-Zamir, A., Elhadidy, O., Yang, H., & Palermo, S.

citation count

  • 7

complete list of authors

  • Roshan-Zamir, Ashkan||Elhadidy, Osama||Yang, Hae-Woong||Palermo, Samuel

publication date

  • January 2016