A scalable decoder architecture for linear congruential LDPC codes Conference Paper

abstract

• Maximal length linear congruential sequence (MLLCS) based LDPC codes have the advantage that the LDPC code graph can be generated at the receiver without having to explicity store the graph. Hence, these codes are advantageous when the same hardware needs to be used for different sets of rates and lengths. In this paper, we reveal an inherent structure in these codes that facilitates parallel implementation of the decoding algorithm. Based on this, we present an architecture for the MLLCS-LDPC decoder that facilitates parallel scalable implementation and joint code-decoder design. 2005 IEEE.

name of conference

• IEEE International Conference on Communications, 2005. ICC 2005. 2005

authors

• Narayanan, Krishna

published proceedings

• ICC 2005: IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-5

author list (cited authors)

• Prabhakar, A., & Narayanan, K.

citation count

• 0

complete list of authors

• Prabhakar, A||Narayanan, K

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• 2013 National Conference on Communications, NCC 2013  Journal

keywords

• Bipartite Graph
• Ldpc Decoder Mllcs
• Parity Check Matrix
• Spa

Digital Object Identifier (DOI)

• 10.1109/icc.2005.1494672

International Standard Book Number (ISBN) 10

• 0-7803-8938-7

start page

• 1911

end page

• 1915

volume

• 3

URL

• http://dx.doi.org/10.1109/icc.2005.1494672