A Memory Efficient Serial Ldpc Decoder Architecture
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We present a memory efficient serial low density parity check(LDPC) decoder that implements a modified Sum Product Algorithm(SPA). The modification is similar to the approximate min constraint presented in [1 ] but differs in hardware implementation to suit a serial architecture. Our main contribution is the proposed architecture that exploits the min constraint to reduce the storage of extrinsic messages which forms the bulk of the hardware. In the proposed design the least reliable bit to check input along with the check sum are the only quantities stored in the decoder. Extrinsic message memory reduction increases with the rate of the code and up to 68% savings is achieved for a rate 9/10 code. Simulation results show that the proposed changes do not degrade the bit error rate performance. © 2005 IEEE.
author list (cited authors)
Prabhakar, A., & Narayanan, K.