A memory efficient serial LDPC decoder architecture Conference Paper

abstract

• We present a memory efficient serial low density parity check(LDPC) decoder that implements a modified Sum Product Algorithm(SPA). The modification is similar to the approximate min constraint presented in [1 ] but differs in hardware implementation to suit a serial architecture. Our main contribution is the proposed architecture that exploits the min constraint to reduce the storage of extrinsic messages which forms the bulk of the hardware. In the proposed design the least reliable bit to check input along with the check sum are the only quantities stored in the decoder. Extrinsic message memory reduction increases with the rate of the code and up to 68% savings is achieved for a rate 9/10 code. Simulation results show that the proposed changes do not degrade the bit error rate performance. 2005 IEEE.

name of conference

• Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

authors

• Narayanan, Krishna

published proceedings

• 2005 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH, AND SIGNAL PROCESSING, VOLS 1-5

author list (cited authors)

• Prabhakar, A., & Narayanan, K.

citation count

• 4

complete list of authors

• Prabhakar, A||Narayanan, K

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference)  Journal

keywords

• Ldpc Decoder Spa
• Memory Efficient Decoding
• Serial Hardware Decoder

Digital Object Identifier (DOI)

• 10.1109/icassp.2005.1416235

International Standard Book Number (ISBN) 10

• 0-7803-8874-7

International Standard Book Number (ISBN) 13

• 9780780388741

start page

• 41

end page

• 44

volume

• 5

URL

• http://dx.doi.org/10.1109/icassp.2005.1416235