Managing the bottlenecks in parallel Gauss-Seidel type algorithms for power flow analysis
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In our earlier papers, the parallelization and implementations of Gauss-Seidel (G-S) algorithms for power flow analysis have been investigated on a Sequent Balance shared memory (SM) machine. In this paper, we generalize the idea to more general computer architectures and demonstrate how to effectively increase the speedup upper bounds of G-S algorithms by properly managing the bottlenecks on both Sequent Balance SM and nCUBE2 distributed memory (DM) machines. We propose a new synchronization scheme which can reduce the synchronization overhead on the Sequent Balance Machine.