A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS Conference Paper uri icon


  • A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm2 core ADC area. 2013 JSAP.

published proceedings

  • IEEE Symposium on VLSI Circuits, Digest of Technical Papers

author list (cited authors)

  • Tabasy, E. Z., Shafik, A., Lee, K., Hoyos, S., & Palermo, S.

complete list of authors

  • Tabasy, EZ||Shafik, A||Lee, K||Hoyos, S||Palermo, S

publication date

  • September 2013