Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable sub-1nm EOT Conference Paper uri icon

abstract

  • For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (≥4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design. © 2008 IEEE.

author list (cited authors)

  • Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Price, J., Majhi, P., ... Jammy, R.

citation count

  • 11

publication date

  • June 2008

publisher