Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable sub-1nm EOT Conference Paper uri icon

abstract

  • For the first time, we provide mechanistic understanding of high gate leakage current on surface channel SiGe pFET with high-k/metal gate to enable sub 1nm EOT. The primary mechanism limiting EOT scaling is Ge enhanced Si oxidation resulting in a thick (1.4nm) SiOx interface layer. A secondary mechanism, Ge doping (4%) in high-k, possibly by up diffusion, also results in higher leakage. With this understanding, we optimized high-k nitridation reducing O and Ge diffusion to achieve EOT=0.91nm directly on SiGe with leakage equivalent to bulk Si. High Ion (1.5x Si), and low subthreshold slope (73mV/dec) are also achieved. This mechanism enables high mobility channel gate dielectric development directly on SiGe without the need for Si cap, simplifying processing and device design. 2008 IEEE.

name of conference

  • 2008 Symposium on VLSI Technology

published proceedings

  • 2008 Symposium on VLSI Technology

author list (cited authors)

  • Huang, J., Kirsch, P. D., Oh, J., Lee, S. H., Price, J., Majhi, P., ... Jammy, R.

citation count

  • 13

complete list of authors

  • Huang, J||Kirsch, PD||Oh, J||Lee, SH||Price, J||Majhi, P||Harris, HR||Gilmer, DC||Kelly, DQ||Sivasubramani, P||Bersuker, G||Heh, D||Young, C||Park, CS||Tan, YN||Goel, N||Park, C||Hung, PY||Lysaght, P||Choi, KJ||Cho, BJ||Tseng, H-H||Lee, BH||Jammy, R

publication date

  • January 2008