Enhanced Performance and SRAM Stability in FinFET with Reduced Process Steps for Source/Drain Doping Conference Paper uri icon


  • Improved static noise margin in SRAM of 18% and decreased intrinsic inverter delay of 6% is demonstrated for the first time in double-gate CMOS finFET with gate-source/drain underlap doping. The excellent results are achieved by optimization of the spacer while simplifying the processing of source/drain region by skipping costly implants. Improved circuit and device performance with reduced processing steps malee finFETs a more attractive option for 32nm technology node and beyond. © 2008 IEEE.

author list (cited authors)

  • Yang, J., Harris, H. R., Hussain, M. M., Sassman, B., Tseng, H., & Jammy, R.

citation count

  • 5

publication date

  • April 2008