Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme Conference Paper uri icon

abstract

  • Using strained SiGe on Si, the threshold voltage of high K PMOS devices is reduced by as much as 300mV. The 80nm devices exhibit excellent short channel characteristics such as DIBL and GIDL. For the first time a dual channel scheme using standard activation anneal temperature is applied that allows La 2O3 capping in NMOS and SiGe channel in PMOS to achieve acceptable values of threshold voltage for high K and metal gates for 32nm node and beyond.

author list (cited authors)

  • Harris, H. R., Kalra, P., Majhi, P., Hussain, M., Kelly, D., Oh, J., ... Jammy, R.

citation count

  • 30

publication date

  • June 2007

publisher