An inverter output filter to mitigate dV/dt effects in PWM drive system Conference Paper uri icon


  • High switching frequencies and small rise times are common with modern switching devices. These parameters, specially the rise time, are known to have undesired side effects such as excessive voltage stress on windings, motor leakage currents, bearing currents, conducted EMI, etc. Furthermore if long cables are used to connect the inverter and the motor, the rapid rise times cause the transmission line effect, which can double the voltage applied to the motor terminals. In this paper a new inverter output filter to mitigate these problems is presented. The filter topology has the advantage of being to easy implementation on existing ASD's as an add-on option and it reduces both common and fferential mode dv/dt simultaneously. Its effectiveness is shown analytically via simulations and by experimental results on a 20 kW ASD.

name of conference

  • APEC 2002 - Applied Power Electronics Conference and Exposition

published proceedings

  • APEC. Seventeenth Annual IEEE Applied Power Electronics Conference and Exposition (Cat. No.02CH37335)

author list (cited authors)

  • Palma, L., & Enjeti, P.

citation count

  • 35

complete list of authors

  • Palma, L||Enjeti, P

publication date

  • January 2002