A Fault-tolerant T-type Three-Level Inverter System Conference Paper uri icon

abstract

  • Field experiences have demonstrated that semiconductor devices are vulnerable to failures (open-& short-circuit). In many critical applications, such failures are unacceptable and high system reliability is required. In this paper, a topology modification for the T-type 3-level inverter is explored to achieve the fault-tolerant operation and enhance the system reliability in the case of device open-circuit or short-circuit failures. With the proposed topology modification (via fewer additional switches), the device failure ride-through performance can be dynamically achieved without degradation of output capacity. Furthermore, the transition principles from normal operations to post-fault operations are detailed, and the reliability enhancement is calculated. The simulation results are included to verify the validity of the modified topology. 2014 IEEE.

name of conference

  • 2014 IEEE Applied Power Electronics Conference and Exposition - APEC 2014

published proceedings

  • 2014 TWENTY-NINTH ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC)

altmetric score

  • 6

author list (cited authors)

  • Zhang, W., Liu, G., Xu, D., Hawke, J., Garg, P., & Enjeti, P.

citation count

  • 12

complete list of authors

  • Zhang, Wenping||Liu, Guangyuan||Xu, Dehong||Hawke, Joshua||Garg, Pawan||Enjeti, Prasad

publication date

  • March 2014