IMAGING LATCH-UP SITES IN CMOS INTEGRATED CIRCUITS USING LASER SCANNING. Conference Paper

abstract

• A novel approach to using laser scanning to analyze latch-up sites in CMOS integrated circuits has been developed. The technique uses a CW laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch up-sites on a high-resolution monitor.

authors

• Weichold, Mark

published proceedings

• Proceedings - Electronic Components and Technology Conference

author list (cited authors)

• Weichold, M. H., & Parker, D. L.

complete list of authors

• Weichold, MH||Parker, DL

publication date

• December 1985

published in

• Electronic Components and Technology Conference  Journal

start page

• 408

end page

• 410