IMAGING LATCH-UP SITES IN CMOS INTEGRATED-CIRCUITS USING LASER SCANNING Academic Article

abstract

• A novel approach to using laser scanning to analyze latch-up sites in complementary metal-oxide semiconductor (CMOS) integrated circuits (IC's) has been developed. The technique employs a continuous wave (CW) laser beam scanned across a CMOS IC as the power to the IC is modulated. Signals corresponding to latch-up currents are detected with a lock-in amplifier and are used to produce a two-dimensional image of latch-up sites on a high resolution monitor. 1986 IEEE

authors

• Weichold, Mark

published proceedings

• IEEE TRANSACTIONS ON COMPONENTS HYBRIDS AND MANUFACTURING TECHNOLOGY

author list (cited authors)

• WEICHOLD, M. H., PARKER, D. L., & FENECH, J. F.

citation count

• 2

complete list of authors

• WEICHOLD, MH||PARKER, DL||FENECH, JF

publication date

• December 1985

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Components, Hybrids and Manufacturing Technology  Journal

keywords

• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware
• Bioengineering

Digital Object Identifier (DOI)

• 10.1109/TCHMT.1985.1136523

start page

• 556

end page

• 558

volume

• 8

issue

• 4

URL

• http://dx.doi.org/10.1109/tchmt.1985.1136523