Pseudo-Circuit: Accelerating Communication for On-Chip Interconnection Networks
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abstract
As the number of cores on a single chip increases with more recent technologies, a packet-switched on-chip interconnection network has become a de facto communication paradigm for chip multiprocessors (CMPs). However, it is inevitable to suffer from high communication latency due to the increasing number of hops. In this paper, we attempt to accelerate network communication by exploiting communication temporal locality with minimal additional hardware cost in the existing state-of-the-art router architecture. We observe that packets frequently traverse through the same path chosen by previous packets due to repeated communication patterns, such as frequent pair-wise communication. Motivated by our observation, we propose a pseudo-circuit scheme. With previous communication patterns, the scheme reserves crossbar connections creating pseudo-circuits, sharable partial circuits within a single router. It reuses the previous arbitration information to bypass switch arbitration if the next flit traverses through the same pseudo-circuit. To accelerate communication performance further, we also propose two aggressive schemes; pseudo-circuit speculation and buffer bypassing. Pseudo-circuit speculation creates more pseudo-circuits using unallocated crossbar connections while buffer bypassing skips buffer writes to eliminate one pipeline stage. Our evaluation results using a cycle-accurate network simulator with traces from SPEComp2001, PARSEC, NAS Parallel Benchmarks, SPECjbb2000, and Splash-2 show 16% improvement in overall network performance and up to 5% reduction in average energy consumption in routers, compared to the state-of-the-art router architecture. Evaluated with synthetic workload traffic, this scheme shows performance improvement by up to 11%. 2010 IEEE.
name of conference
2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture
