Peak power control for a QoS capable on-chip network Conference Paper uri icon


  • In recent years integrating multiprocessors in a single chip is emerging for supporting various scientific and commercial applications, with diverse demands to the underlying on-chip networks. Communication traffic of these applications makes routers greedy to acquire more power such that the total consumed power of the networkmay exceed the supplied power and cause reliability problems. To ensure high performance and power constraint satisfaction, the on-chip network must have a peak power control mechanism. In this paper, we propose a credit-based peak power control scheme to assure power consumption to be under the given peak power constraint, without performance degradation. The peak power control scheme efficiently regulates each flow's injection rate at the sender to minimize performance penalty. We have two different throttling schemes for real-time traffic and best-effort traffic; a rate-based throttling and an energy-budget based throttling, respectively. The simulation results on mesh networks show that the credit-based peak power control effectively prevents performance degradation and meets the peak power constraint. © 2005 IEEE.

name of conference

  • 2005 International Conference on Parallel Processing (ICPP'05)

published proceedings


author list (cited authors)

  • Jin, Y. H., Kim, E. J., & Yum, K. H.

citation count

  • 6

complete list of authors

  • Jin, YH||Kim, EJ||Yum, KH

publication date

  • January 2005