Efficient Data Packet Compression for Cache Coherent Multiprocessor Systems Conference Paper uri icon

abstract

  • Multiprocessor systems have been popular for their high performance not only for server markets but also for computing environments for general users. With the increased software complexity, networking overheads in multiprocessor systems are becoming one of the most influential factors in overall system performance. In this paper, we attempt to reduce communication overheads through a data packet compression technique integrating a cache coherence protocol. Here we propose Variable Size Compression (VSC) scheme that compresses or completely eliminates data packets while harmonizing with existing cache coherence protocols. Simulation results show approximately 23 of improvement on average in terms of overall system performance when compared with the most recent compression scheme. VSC also improves performance by 20 on average in terms of cache miss latency. © 2012 IEEE.

name of conference

  • 2012 Data Compression Conference

published proceedings

  • 2012 DATA COMPRESSION CONFERENCE (DCC)

author list (cited authors)

  • An, B. S., Lee, M., Yum, K. H., & Kim, E. J.

citation count

  • 5

complete list of authors

  • An, Baik Song||Lee, Manhee||Yum, Ki Hwan||Kim, Eun Jung

publication date

  • April 2012