A Hybrid Buffer Design with STT-MRAM for On-Chip Interconnects
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As the chip multiprocessor (CMP) design moves toward many-core architectures, communication delay in Network-on-Chip (NoC) has been a major bottleneck in CMP systems. Using high-density memories in input buffers helps to reduce the bottleneck through increasing throughput. Spin-Torque Transfer Magnetic RAM (STT-MRAM) can be a suitable solution due to its nature of high density and near-zero leakage power. But its long latency and high power consumption in write operations still need to be addressed. We explore the design issues in using STT-MRAM for NoC input buffers. Motivated by short intra-router latency, we use the previously proposed write latency reduction technique sacrificing retention time. Then we propose a hybrid design of input buffers using both SRAM and STT-MRAM to hide the long write latency efficiently. Considering that simple data migration in the hybrid buffer consumes more dynamic power compared to SRAM, we provide a lazy migration scheme that reduces the dynamic power consumption of the hybrid buffer. Simulation results show that the proposed scheme enhances the throughput by 21% on average. © 2012 IEEE.
name of conference
2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS)
2012 IEEE/ACM Sixth International Symposium on Networks-on-Chip
author list (cited authors)
Jang, H., An, B. S., Kulkarni, N., Yum, K. H., & Kim, E. J.
complete list of authors
Jang, Hyunjun||An, Baik Song||Kulkarni, Nikhil||Yum, Ki Hwan||Kim, Eun Jung