Highly parallel VLSI architectures for linear convolution Conference Paper uri icon


  • This paper presents highly parallel VLSI structures for linear convolution. Our methodology implements Toom's algorithm and is based on mapping a modified version of the tensor product factorization proposed by Granata et. al. [4]. The resulting networks have very simple structure, highly regular topology, and use simple bit-serial devices. Additionally, the proposed networks have very small depth and contain only a single stage of multipliers, while all other stages contain adders only.

author list (cited authors)

  • Elnaggar, A., Alnuweiri, H. M., & Ito, M. R.

publication date

  • January 1, 1995 11:11 AM