This paper proposes a general class of scalable ATM switches based on a buffered fat-tree structures. A distinguishing feature of the proposed switches is that they have been designed to handle nonuniform (as well as uniform) traffic robustly while fully utilizing switch resources (buffers and bandwidth). The buffer-size and bandwidth of each stage of a switch are specified by parameters which can be computed to optimize the switch with respect to cost, utilization, cell-loss, and total delay. The paper also develops a discrete-time approximate model for analyzing the performance of the proposed switch. In particular, the analysis determines the influence of various design parameters on optimizing the switch performance. Additionally, the paper addresses the problem of dimensioning the switch to guarantee certain quality-of-service requirements while minimizing buffer-space and switch delays.
