A Single Parity Check Forward Error Correction Method for High Speed I/O Conference Paper uri icon


  • 2014 IEEE. Some proposed high speed wireline communications make use of an ADC front end to allow a feedforward equalizer (FFE) to compensate for the frequency dependent loss of the channel. High precision ADCs are expensive in terms of power. The FFE block performs multiplication and addition operations at high speed and further increases the power consumption. This paper proposes a simple forward error correction method by which the ADC resolution and the equalizer complexity can be reduced. A single parity check code implemented together with a threshold detector can provide single error correction capability. With this error correction capability, the number of taps required in the FFE block is shown to be reduced to 3 taps from 6 taps for a channel with 15dB insertion loss at 5GHz frequency with the data rate being 20Gb/s. The effective number of bits (ENOB) required from the ADC is also shown to reduce to about 3.5 bits from 6 bits. The high rate of the code and the very simple decoder architecture make this error correction mechanism well suited for the wireline application.

name of conference

  • 2014 IEEE Global Conference on Signal and Information Processing (GlobalSIP)

published proceedings


author list (cited authors)

  • Kiran, S., Hoyos, S., & Palermo, S.

citation count

  • 2

complete list of authors

  • Kiran, Shiva||Hoyos, Sebastian||Palermo, Samuel

publication date

  • January 2014