Reduced area discrete-time down-sampling filter embedded with windowed integration samplers Academic Article

abstract

• A technique to implement a discrete-time (DT) sinc3 2 filter for windowed integration samplers is proposed. The topology reduces the idle time of the integration capacitors at the expense of a small complexity overhead in the clock generation, thereby saving 33 of the die area compared to the currently existing topology. Circuit level simulations in 45nm CMOS technlogy shows good agreement with the predicted behaviour obtained from the analaysis. 2010 The Institution of Engineering and Technology.

authors

• Hoyos, Sebastian

published proceedings

• ELECTRONICS LETTERS

author list (cited authors)

• Raviprakash, K., Saad, R., & Hoyos, S.

citation count

• 1

complete list of authors

• Raviprakash, K||Saad, R||Hoyos, S

publication date

• June 2010

publisher

• Institution of Engineering and Technology (IET)  Publisher

published in

• Electronics Letters  Journal

keywords

• 40 Engineering
• 4006 Communications Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1049/el.2010.1038

URI

• https://hdl.handle.net/1969.1/ETD-TAMU-2010-08-8396

start page

• 828

end page

• 829

volume

• 46

issue

• 12

URL

• http%3A%2F%2Fdx.doi.org%2F10.1049%2Fel.2010.1038