A Fully On-Chip 10Gb/s CDR in a Standard 0.18 μm CMOS Technology Conference Paper uri icon


  • A fully integrated OC-192 clock-data recovery (CDR) architecture in standard 0.18μm CMOS is described. The CDR integrates the large filter capacitor and satisfies SONET jitter tolerance requirements with a total power dissipation (including the buffers) of 290mW. The measured RMS jitter of the recovered data is 0.74ps with a bit-error rate (BER) less than 10-12 when the input 215-1 PRBS data pattern has a total horizontal eye closure of 0.54 UIpp due to the added ISI distortion by passing data through 9 inches FR4 PCB trace. © 2007 IEEE.

author list (cited authors)

  • Li, J., & Silva-Martinez, J.

citation count

  • 1

publication date

  • June 2007