Strategic test cost reduction with on-chip measurement circuitry for RF transceiver front-ends An overview Conference Paper uri icon

abstract

  • This paper addresses key technical and economic issues in the design of on-chip measurement circuitry that can be utilized to reduce the cost of testing. A brief outline is provided for research work related to analog/RF built-in selftest (BIST), on-chip instrumentation, and testing requirements of RF front-end blocks. The overview is intended to present test cost reduction requirements and techniques from a circuit design perspective. One promising approach for the test of fully-integrated RF transceiver front-ends with on-chip loopback and strategically placed power detectors along the RF signal path will be discussed as a demonstrative example of the presented concepts. The main focus in this paper is on reported work that is relevant to improvement of test coverage and cost reduction for on-wafer functional test with minimal area overhead and test time. 2006 IEEE.

name of conference

  • 2006 49th IEEE International Midwest Symposium on Circuits and Systems

published proceedings

  • IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II

author list (cited authors)

  • Onabajo, M., Fernandez, F., Silva-Martinez, J., & Sanchez-Sinencio, E.

citation count

  • 6

complete list of authors

  • Onabajo, Marvin||Fernandez, Felix||Silva-Martinez, Jose||Sanchez-Sinencio, Edgar

publication date

  • August 2006