Efficient clock recovery architecture Academic Article uri icon


  • © 1998 IEEE. In this paper, a clock recovery architecture is proposed. Although it employs a single high frequency loop, the structure behaves as the typical double loop clock recovery system. The proposed topology uses a high frequency phase detector, a low frequency loop and avoids the use of quadrature VCOs.

author list (cited authors)

  • Mendez-Rivera, M., Valero-Lopez, A., Silva-Martinez, J., & Sanchez-Sinencio, E.

citation count

  • 1

publication date

  • January 1998