A 16mW, 2.23~2.45GHz Fully Integrated PLL with Novel Prescaler and Loop Filter in 0.35m CMOS Conference Paper uri icon

abstract

  • A 3mW inherently glitch-free phase-switching prescaler and a loop filter with a 0.2mW capacitance multiplier are proposed for a PLL synthesizer in 0.35m CMOS. The noise folding is minimized by optimal design of modulator and minimized PLL nonlinearities. The synthesizer has a 9.4% tuning range of 2.23-2.45GHz. The phase noise is -90dBc/Hz at 10kHz, and -128dBe/Hz at 10MHz offset.

name of conference

  • IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003

published proceedings

  • IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2003

author list (cited authors)

  • Shu, K., Snchez-Sinencio, E., Silva-Martnez, J., & Embabi, S.

citation count

  • 0

complete list of authors

  • Shu, Keliu||Sánchez-Sinencio, Edgar||Silva-Martínez, José||Embabi, Sherif HK

publication date

  • January 2003