Impact of the Errors in the PMU Response on Synchrophasor-Based Fault Location Algorithms Conference Paper uri icon

abstract

  • © 2016 IEEE. Over the past decades, many synchrophasor applications have been developed but the performance under various PMU errors has not been explored and is unknown for most applications. This paper discusses the impact of PMU measurement errors and limitations originated from hardware implementation of various phasor estimation algorithms on the accuracy of the synchrophasor-based fault location application, in particular on the fault location algorithm that uses synchronized phasors at both line terminals. The application test procedure is implemented on a simple two-bus system modeled in ATP-EMTP with different types of fault scenarios simulated and various real PMUs exposed to the fault signals through hardware-in-the-loop testing. Results acquired from such evaluations provide invaluable knowledge about limitations and vulnerabilities of synchrophasor end-use applications.

author list (cited authors)

  • Becejac, T., Dehghanian, P., & Kezunovic, M.

publication date

  • January 1, 2016 11:11 AM

publisher