Impact of the Errors in the PMU Response on Synchrophasor-Based Fault Location Algorithms Conference Paper

abstract

• 2016 IEEE. Over the past decades, many synchrophasor applications have been developed but the performance under various PMU errors has not been explored and is unknown for most applications. This paper discusses the impact of PMU measurement errors and limitations originated from hardware implementation of various phasor estimation algorithms on the accuracy of the synchrophasor-based fault location application, in particular on the fault location algorithm that uses synchronized phasors at both line terminals. The application test procedure is implemented on a simple two-bus system modeled in ATP-EMTP with different types of fault scenarios simulated and various real PMUs exposed to the fault signals through hardware-in-the-loop testing. Results acquired from such evaluations provide invaluable knowledge about limitations and vulnerabilities of synchrophasor end-use applications.

name of conference

• 2016 North American Power Symposium (NAPS)

authors

• Kezunovic, Mladen

published proceedings

• 2016 NORTH AMERICAN POWER SYMPOSIUM (NAPS)

author list (cited authors)

• Becejac, T., Dehghanian, P., & Kezunovic, M.

citation count

• 10

complete list of authors

• Becejac, Tamara||Dehghanian, Payman||Kezunovic, Mladen

publication date

• January 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n2163-4939ISSN  Journal

keywords

• Application Error
• Fault Location
• Hardware-in-the-loop
• Phasor Measurement Unit
• Testing
• Trustfulness

Digital Object Identifier (DOI)

• 10.1109/naps.2016.7747946

International Standard Book Number (ISBN) 13

• 9781509032709

start page

• 1

end page

• 6

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fnaps.2016.7747946

user-defined tag

• 7 Affordable and Clean Energy