Hardware Implementation of Corner2 Lossless Compression Algorithm for Maskless Lithography Systems
Conference Paper
Overview
Research
Identity
Additional Document Info
Other
View All
Overview
abstract
The data delivery throughput of maskless lithography systems can be improved by applying a lossless image compression algorithm to the layout images and using a lithography writer that contains a decoding circuit packed in single silicon to decode the compressed image on-the-fly. In our past research we have introduced Corner2, a layout image compression algorithm which achieved significantly better performance in all aspects (compression ratio, encoding/decoding speed, decoder memory requirement) than Block C4. In this paper, we present the synthesis results of the Corner2 decoder for FPGA implementation. 2012 Copyright SPIE.