Background ADC Calibration in Digital Domain Conference Paper uri icon

abstract

  • A 100MS/s pipelined ADC is digitally calibrated by a slow ADC using a least-mean-square (LMS) algorithm. Both linear and nonlinear memoryless residue gain errors of the pipeline stages are adaptively corrected. With a 411kHz sinusoidal input, the peak SNDR Improves from 28dB to 59dB and the SFDR Improves from 29dB to 68dB. The complete 0.13m ADC SoC occupies a die size of 3.7mm 4.7mm, and consumes a total power of 448mW. 2008 IEEE.

name of conference

  • 2008 IEEE Custom Integrated Circuits Conference

published proceedings

  • PROCEEDINGS OF THE IEEE 2008 CUSTOM INTEGRATED CIRCUITS CONFERENCE

author list (cited authors)

  • Tsang, C., Chiu, Y., Vanderhaegen, J., Hoyos, S., Chen, C., Brodersen, R., & Nikolic, B.

citation count

  • 39

complete list of authors

  • Tsang, Cheongyuen||Chiu, Yuri||Vanderhaegen, Johan||Hoyos, Sebastian||Chen, Charles||Brodersen, Robert||Nikolic, Borivoje

publication date

  • January 2008