Clock-Jitter-Tolerant Wideband Receivers: An Optimized Multichannel Filter-Bank Approach Academic Article uri icon


  • Clock jitter is one of the most fundamental obstacles in realizing future generations of wideband receivers. Stringent jitter specifications in the sampling clocks of high-performance single-channel and multichannel time-interleaved analog-to-digital converters severely limit the evolution of baseband receivers. This paper presents an analytical framework for the design of clock-jitter-tolerant low-order multichannel filter-bank receivers, with techniques to dramatically lower the sampling-clock-jitter specifications. Although it is well understood that high-order frequency-channelized receivers provide higher tolerance to sampling jitter, this paper shows that low-order bandwidth-optimized multichannel receivers can achieve similar sampling-jitter tolerance. Additionally, this paper presents design tradeoffs and specifications of an example multichannel receiver that can process a 5-GHz baseband signal with 40 dB of signal-to-noise-ratio using sampling clocks that can tolerate up to 5 ps rms clock jitter. In comparison, existing architectures based on time-interleaving require 0.5 ps rms clock jitter for the given specifications. This extreme jitter tolerance allows for relaxed design of clocking systems, which averts a major roadblock in future wideband- communication-receiver development and provides the potential to enable several high-data-rate communication applications. 2011 IEEE.

published proceedings


author list (cited authors)

  • Hoyos, S., Pentakota, S., Yu, Z., Ghany, E., Chen, X. i., Saad, R., Palermo, S., & Silva-Martinez, J.

citation count

  • 14

complete list of authors

  • Hoyos, Sebastian||Pentakota, Srikanth||Yu, Zhuizhuan||Ghany, Ehab Sobhy Abdel||Chen, Xi||Saad, Ramy||Palermo, Samuel||Silva-Martinez, Jose

publication date

  • February 2011