A 0.8V, 560fJ/bit, 14Gb/s injection-locked receiver with input duty-cycle distortion tolerable edge-rotating 5/4X sub-rate CDR in 65nm CMOS Conference Paper uri icon


  • A quarter-rate forwarded-clock receiver utilizes an edge-rotating 5/4X sub-rate CDR for improved jitter tolerance with low power overhead relative to conventional 2X oversampling CDR systems. Low-voltage operation is achieved with efficient quarter-rate clock generation from an injection-locked oscillator (ILO) and through automatic independent phase rotator control that optimizes timing margin of each input quantizer in the presence of receive-side clock static phase errors and transmitter duty-cycle distortion (DCD). Fabricated in GP 65nm CMOS, the receiver operates up to 16Gb/s with a BER<10-12, achieves a 1MHz phase tracking bandwidth, tolerates 50%UIpp DCD on input data, and has 14Gb/s energy efficiency of 560fJ/bit at V DD=0.8V. 2014 IEEE.

name of conference

  • 2014 Symposium on VLSI Circuits Digest of Technical Papers

published proceedings

  • 2014 Symposium on VLSI Circuits Digest of Technical Papers

author list (cited authors)

  • Li, H., Chen, S., Yang, L., Bai, R., Hu, W., Zhong, F. Y., Palermo, S., & Chiang, P. Y.

citation count

  • 12

complete list of authors

  • Li, Hao||Chen, Shuai||Yang, Liqiong||Bai, Rui||Hu, Weiwu||Zhong, Freeman Y||Palermo, Samuel||Chiang, Patrick Yin

publication date

  • January 2014