A Low Noise 13 GHz Power Efficient 16/17 Prescaler with Rail to Rail Output Amplitude Conference Paper uri icon


  • A state of the art 16/17 prescaler using Current Mode Logic (CML) D-Flip Flops, CMOS inverters, and transmission gates for the .18μ TSMC process with a 1.8 V supply voltage is presented. The prescaler consists of a 4/5 synchronous core and a feedback loop which modulates the 4/5 core to produce a division ratio of 16/17. Instead of employing power hungry CML, the feedback circuit takes advantage of low power NOR and AND gates realized in Transmission Gate Logic (TGL) to reduce the power consumption. To the best of our knowledge, this technique has never been used in a high frequency prescaler before. Additionally, this work will serve as a comprehensive description of the numerous considerations of prescaler design including explanation of gate-level design and transistor level optimization. Furthermore, digital circuit output is efficiently buffered with CMOS inverters for rail-to-rail operation, maximizing slew rate which minimizes phase noise. The simulated phase noise is -150 dBc/Hz @ 1 MHz and the input bandwidth is 2 GHz (11 GHz and 13 GHz). The power consumption of the entire prescaler is 18.5 mW. All of the above results were obtained from post-layout simulations. Circuit layout has been completed and sent for fabrication. ©2007 IEEE.

author list (cited authors)

  • Eschenko, E., Candidate, M. S., & Entesari, K.

citation count

  • 5

publication date

  • August 2007