A 1.6GHz/4.8GHz Dual-Band CMOS Fractional-N Frequency Synthesizer for S-Band Radio Applications Conference Paper uri icon


  • A 1.6GHz/ 4.8GHz fractional-N frequency synthesizer in 0.18-μm CMOS technology is presented in this paper. Its purpose is to generate the local oscillator (LO) signals for a fully integrated S-Band transceiver with a direct-conversion receiver (RX) and a dual up-conversion transmitter (TX) to avoid the frequency pulling problem. The synthesizer achieves phase noise of -141.3dBc/Hz at 1.62GHz and -132.6dBc/Hz at 4.86GHz (both at 3MHz offset), with reference spurs <-70.2dBc for the lower band (LB) and <-63.8dBc for the higher band (HB). Total power consumption is 18.2-22.7mW from a 1V supply for the VCO and 1.8V for the other synthesizer blocks. © 2014 IEEE.

author list (cited authors)

  • Bajestan, M. M., Foli, E., Hedayati, H., & Entesari, K.

citation count

  • 0

publication date

  • June 2014