A 2.8-4.3GHz Wideband Fractional-N Sub-Sampling Synthesizer with −112.5dBc/Hz in-Band Phase Noise Conference Paper uri icon


  • © 2016 IEEE. A 2.8-4.3GHz low noise fractional-N subsampling frequency synthesizer in 40nm CMOS technology is presented in this paper. The reference sampling clock is modulated by a 10-bit edge modulator to achieve fractional phase lock. A novel fast two-step background calibration is used to correct gain errors in the edge modulator, reducing fractional spurs. For a 3.75GHz carrier, the synthesizer achieves 376fs rms jitter with a worst case fractional spur of -48.3dBc. The in-band phase noise at 200kHz offset is -112.5dBc/Hz. The system consumes a total power of 9.18mW from a 1.1V supply and occupies an area of 0.41mm2.

author list (cited authors)

  • Bajestan, M. M., Attah, H., & Entesari, K.

citation count

  • 4

publication date

  • May 2016