A 2.8-4.3GHz Wideband Fractional-N Sub-sampling Synthesizer with-112.5dBc/Hz In-Band Phase Noise Conference Paper

abstract

• 2016 IEEE. A 2.8-4.3GHz low noise fractional-N subsampling frequency synthesizer in 40nm CMOS technology is presented in this paper. The reference sampling clock is modulated by a 10-bit edge modulator to achieve fractional phase lock. A novel fast two-step background calibration is used to correct gain errors in the edge modulator, reducing fractional spurs. For a 3.75GHz carrier, the synthesizer achieves 376fs rms jitter with a worst case fractional spur of -48.3dBc. The in-band phase noise at 200kHz offset is -112.5dBc/Hz. The system consumes a total power of 9.18mW from a 1.1V supply and occupies an area of 0.41mm2.

name of conference

• 2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

authors

• Entesari, Kamran

published proceedings

• 2016 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS SYMPOSIUM (RFIC)

author list (cited authors)

• Bajestan, M. M., Attah, H., & Entesari, K.

citation count

• 7

complete list of authors

• Bajestan, Masoud Moslehi||Attah, Hubert||Entesari, Kamran

publication date

• May 2016

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Digest of Papers - IEEE Radio Frequency Integrated Circuits Symposium  Journal

keywords

• Fractional-n Synthesizer
• Low Jitter
• Low Phase Noise
• Phase-locked-loop (pll)
• Sub-sampling Pll
• Wideband

Digital Object Identifier (DOI)

• 10.1109/rfic.2016.7508267

International Standard Book Number (ISBN) 13

• 9781467386500

start page

• 126

end page

• 129

volume

• 2016-July

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Frfic.2016.7508267