A 43-mW MASH 2-2 CT $Sigma Delta$ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS Academic Article uri icon


  • © 2016 IEEE. This paper proposes a multistage noise-shaping continuous-time sigma-delta modulator (CT Σ Δ M) with on-chip RC time constant calibration circuits, multiple feedforward interstage paths, and a fully integrated noise-cancellation filter (NCF). The core modulator architecture is a cascade of two single-loop second-order CT Σ Δ M stages, each of which consists of an integrator-based active-RC loop filter, current-steering feedback digital-to-analog converters, and a 4-b flash quantizer. On-chip RC time constant calibration circuits and high-gain multistage operational amplifiers are realized to mitigate quantization noise leakage due to process variation. Multiple feedforward interstage paths are introduced to: 1) synthesize a fourth-order noise transfer function with dc zeros; 2) simplify the design of NCF; and 3) reduce signal swings at the second-stage integrator outputs. Fully integrated in 40-nm CMOS, the prototype chip achieves 74.4 dB of signal-to-noise-and-distortion ratio (SNDR), 75.8 dB of signal-to-noise ratio, and 76.8 dB of dynamic range in 50.3 MHz of bandwidth (BW) at 1 GHz of sampling frequency with 43 mW of power consumption (P) from 1.1/1.15/2.5-V power supplies. It does not require external software calibration and possesses minimal out-of-band signal transfer function peaking. The figure-of-merit (FOM), defined as FOM= SNDR + 10 × log10(BW/P), is 165.1 dB.

author list (cited authors)

  • Edward, A., Liu, Q., Briseno-Vidrios, C., Kinyua, M., Soenen, E. G., Karşılayan, A. I., & Silva-Martinez, J.

citation count

  • 18

publication date

  • November 2016