Fast timing recovery for linearly and non-linearly modulated systems
Conference Paper
Overview
Identity
Additional Document Info
Other
View All
Overview
abstract
Digital phase-lock loop (PLL) is often used for timing recovery. Some non-data-aided timing error detectors occasionally cause hangup problem in the digital PLL. In this paper we introduce a new two-step anti-hangup timing recovery scheme. By simulations, we show that this enhanced scheme greatly reduces the probability of hangup and speeds up timing recovery for both linearly and nonlinearly modulated systems. 2004 IEEE.
name of conference
Conference Record of the Thirty-Eighth Asilomar Conference on Signals, Systems and Computers, 2004.