A 10Gb/s Hybrid ADC-Based Receiver with Embedded 3-Tap Analog FFE and Dynamically-Enabled Digital Equalization in 65nm CMOS Conference Paper uri icon

abstract

  • 2015 IEEE. ADC-based receivers are currently being proposed in high-speed serial link applications to enable flexible, complex, and robust digital equalization in order to support operation over high loss channels [1-3]. However, the power dissipation of the ADC, as well as the digital equalization that follows, is a major concern for wireline receiver applications [3]. In this work, a hybrid ADC-based receiver architecture is presented that introduces innovations in both the ADC and the digital equalizer design. First, an analog 3-tap feed-forward equalizer (FFE) is efficiently embedded into a 6b time-interleaved SAR ADC, allowing for reductions in both ADC resolution and digital equalizer complexity. Second, significant power reduction is achieved by detecting reliable symbols at the ADC output and dynamically enabling/disabling the digital equalizer.

name of conference

  • 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers

published proceedings

  • 2015 IEEE INTERNATIONAL SOLID-STATE CIRCUITS CONFERENCE DIGEST OF TECHNICAL PAPERS (ISSCC)

author list (cited authors)

  • Shafik, A., Tabasy, E. Z., Cai, S., Lee, K., Hoyos, S., & Palermo, S.

citation count

  • 13

complete list of authors

  • Shafik, Ayman||Tabasy, Ehsan Zhian||Cai, Shengchang||Lee, Keytaek||Hoyos, Sebastian||Palermo, Samuel

publication date

  • January 2015