DESIGN OF A NEW COMPACT AND REGULAR 8 X 8 MULTIPLIER USING REDUNDANT BINARY NUMBER REPRESENTATION
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A new compact and highly regular redundant binary multiplier employing SD number representation has been developed. The n-bit multiplication time required by the multiplier is proportional to log2n. A modified redundant-to-binary converter has also been proposed, which results in a reduction of the delay time and size of the multiplier. The multiplier adopts a hybrid V-L adder tree structure. The modified Booth's algorithm is employed to reduce the number of partial products to half. For an 88 multiplier employing the modified converter, the chip size is 20963256m2. The multiplication time is measured as 48.9ns using a 2m design rule. We estimated the multiplication time of a 1616 multiplier to be 70ns using a 2m design rule, and about 35ns using a 1m design rule and double layer metal wiring. The estimation of the delay time of a 3232 multiplier is about 70ns using a 1m design rule and double layer metal wiring.
name of conference
Proceedings of 36th Midwest Symposium on Circuits and Systems
PROCEEDINGS OF THE 36TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1 AND 2
author list (cited authors)
GOPALAN, M., LU, M., & YIN, J. M.
complete list of authors
GOPALAN, M||LU, M||YIN, JM