An efficient implementation of high-accuracy finite difference computing engine on FPGAs
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abstract
Finite Difference (FD) methods are the most prevalent numerical modelling algorithms for evaluating initial or boundary value problems in scientific and engineering applications. Unfortunately, simulating time evolutions for transient physical phenomenon is computationally demanding and data-intensive. In this paper, we introduce an efficient implementation of FD computing engine on FPGA-based Reconfigurable Computing (RC) platform. Instead of following the formal high-order FD expressions with standard IEEE-754 compliant floatingpoint arithmetic units, we propose a new class of optimized finite-accurate FD schemes, whose FD coefficients are optimized to be represented with only a few binary bits without deteriorating numerical accuracy criterions. Furthermore, in order to simplify the implementation of floating-point summations, we replace the conventional costly floating-point adder tree by a floating-point/fixed- point hybrid accumulator using group-alignment technology. The resulting fully-pipelined FD computing engine with finite accurate coefficients can provide us similar or even better worst case relative and absolute rounding errors than standard floating-point arithmetic, but consumes only a fraction of hardware resources. This new design can be easily applied to our previous work [1] [4] and result in a more efficient and compact implementation with much higher computational performance. 2006 IEEE.
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IEEE 17th International Conference on Application-specific Systems, Architectures and Processors (ASAP'06)
