publication venue for
- On-chip Parallel Photonic Reservoir Computing using Multiple Delay lines 2020
- Building a Low Latency, Highly Associative DRAM Cache with the Buffered Way Predictor 2016
- Intra-Clustering: Accelerating On-Chip Communication for Data Parallel Architectures 2015
- Composite Confidence Estimators for Enhanced Speculation Control 2009
- Controlling the Power and Area of Neural Branch Predictors for Practical Implementation in High-Performance Processors* *A subset of the ideas presented in this paper appeared in an earlier workshop with unpublished proceedings 2006
- Chained In-Order/Out-of-Order DoubleCore Architecture 2005
- Adaptive compressed caching: Design and implementation 2003
- Improving error bounds for multipole-based treecodes 1998