Preconditioned iterative solvers for inductance extraction of VLSI circuits
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abstract
Parasitic extraction techniques are used to estimate signal delay in VLSI circuits. Inductance extraction is a critical component of the parasitic extraction process that involves estimation of on-chip inductive effects with high accuracy. The problem requires the solution of a large, dense, complex linear system of equations, where the unknown current must satisfy the constraint imposed by Kirchoff's current law. In this paper, we describe a solenoidal basis method to transform the constrained linear system into an unconstrained one. The method uses discrete local solenoidal flows to represent the unknown current, and to obtain a reduced linear system. The paper proposes preconditioning techniques that do not require explicit construction of the reduced system. Numerical experiments are presented to illustrate the effectiveness of the preconditioning approach. Comparisons with a well-known inductance extraction package are provided to highlight the advantages of the proposed scheme. 2007 Society for Industrial and Applied Mathematics.
