Full on-chip CMOS low-dropout voltage regulator Academic Article

abstract

• This paper proposes a solution to the present bulky external capacitor low-dropout (LDO) voltage regulators with an external capacitorless LDO architecture. The large external capacitor used in typical LDOs is removed allowing for greater power system integration for system-on-chip (SoC) applications. A compensation scheme is presented that provides both a fast transient response and full range alternating current (ac) stability from 0- to 50-mA load current even if the output load is as high as 100 pF. The 2.8-V capacitorless LDO voltage regulator with a power supply of 3 V was fabricated in a commercial 0.35-m CMOS technology, consuming only 65 A of ground current with a dropout voltage of 200 mV. Experimental results demonstrate that the proposed capacitorless LDO architecture overcomes the typical load transient and ac stability issues encountered in previous architectures. 2007 IEEE.

authors

• Silva-Martinez, Jose

published proceedings

• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

altmetric score

• 9

author list (cited authors)

• Milliken, R. J., Silva-Martinez, J., & Sanchez-Sinencio, E.

citation count

• 379

publication date

• September 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• Analog Circuits
• Capacitorless Low Dropout (ldo)
• Dc-dc Regulator
• Fast Path
• Ldo Voltage Regulators
• Transient Compensation.

Digital Object Identifier (DOI)

• 10.1109/TCSI.2007.902615

start page

• 1879

end page

• 1890

volume

• 54

issue

• 9

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftcsi.2007.902615