Design Techniques to Improve Blocker Tolerance of Continuous-Time Delta Sigma ADCs
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2014 IEEE. Design techniques to provide robustness against loop saturation due to blockers in modulators are presented. Loop overload detection and correction are employed to improve the analog-to-digital converters (ADCs) tolerance to strong blockers; a fast overload detector activates the input attenuator, maintaining the ADC in linear operation. To further improve ADCs blocker tolerance, a minimally invasive integrated low-pass filter that reduces the most critical adjacent/alternate channel blockers is implemented. Measurement results show that the proposed ADC implemented in a 90 nm CMOS process achieves 69 dB dynamic range over a 20 MHz bandwidth with a sampling frequency of 500 MHz and 17.1 mW of power consumption. The alternate channel blocker tolerance at the most critical frequency is as high as -5.5 dBFS while the conventional feedforward modulator becomes unstable at -23.5 dBFS of blocker power. The proposed blocker rejection techniques are minimally invasive and take less than 0.3 s to settle after a strong agile blocker appears.
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
author list (cited authors)
Geddada, H. M., Park, C., Jeon, H., Silva-Martinez, J., Karsilayan, A. I., & Garrity, D.
complete list of authors
Geddada, Hemasundar Mohan||Park, Chang-Joon||Jeon, Hyung-Joon||Silva-Martinez, Jose||Karsilayan, Aydin Ilker||Garrity, Douglas