Steady-state analysis of phase-locked loops using binary phase detector Academic Article

abstract

• Phase-locked loops (PLLs) using binary phase detec tors (BPDs) are modeled and analyzed in this paper. Steady-state behavior for PLLs based on BPDs (BPLs) using first- and second-order loop filters is characterized using transient waveform equations. It is shown that BPLL has a range of oscillation modes in steady state when there is no input jitter. The BPLL is most likely to operate at the most stable oscillation mode (MSOM) under the disturbance of random input jitter. The MSOM is determined by evaluating the relative stability of all the modes. The expected value of the output jitter amplitude is derived and its dependence on the loop parameters is analyzed. 2007, IEEE. All rights reserved.

authors

• Karsilayan, Aydin
• Silva-Martinez, Jose

published proceedings

• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS

author list (cited authors)

• Cheng, S., Tong, H., Silva-Martinez, J., & Karsilayan, A. I.

citation count

• 10

complete list of authors

• Cheng, Shanfeng||Tong, Haitao||Silva-Martinez, Jose||Karsilayan, Aydin Ilker

publication date

• June 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• Bang-bang Phase Detector (bpd)
• Binary Phase-detector
• Clock-and-data Recovery (cdr)
• Phase-locked Loop (pll)

Digital Object Identifier (DOI)

• 10.1109/TCSII.2007.894429

start page

• 474

end page

• 478

volume

• 54

issue

• 6

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftcsii.2007.894429