Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm Academic Article

abstract

• The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

authors

• Narayanan, Krishna

published proceedings

• IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS

altmetric score

• 3

author list (cited authors)

• Mondragon-Torres, A. F., Sanchez-Sinencio, E., & Narayanan, K. R.

citation count

• 10

complete list of authors

• Mondragon-Torres, AF||Sanchez-Sinencio, E||Narayanan, KR

publication date

• October 2003

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Circuits and Systems I: Regular Papers  Journal

keywords

• Analog Processing
• Floating-gate (fg) Mos Transistors
• Parallel Concatenated Convolutional Codes (pccc)
• Soft Input Soft Output (siso)
• Translinear Circuits
• Turbo Codes

Digital Object Identifier (DOI)

• 10.1109/TCSI.2003.817763

start page

• 1256

end page

• 1269

volume

• 50

issue

• 10

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftcsi.2003.817763