Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm Academic Article uri icon


  • The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.

published proceedings

  • IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications

altmetric score

  • 3

author list (cited authors)

  • Mondragon-Torres, A. F., Sanchez-Sinencio, E., & Narayanan, K. R.

citation count

  • 10

complete list of authors

  • Mondragon-Torres, AF||Sanchez-Sinencio, E||Narayanan, KR

publication date

  • October 2003