Floating-gate analog implementation of the additive soft-input soft-output decoding algorithm
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The soft-input soft-output algorithm is used to iteratively decode concatenated codes. To efficiently implement this algorithm, an additive form in the logarithmic domain is employed. A novel analog implementation using CMOS translinear circuits is proposed. A multiple-input floating-gate CMOS transistor working in the subthreshold region is used as the main translinear computing element. The proposed approach allows a direct mapping between the decoding algorithm and the circuit implementation. Experimental CMOS chip results are in good agreement with theoretical and simulation results.
author list (cited authors)
Mondragon-Torres, A. F., Sanchez-Sinencio, E., & Narayanan, K. R.