Thermography and neural networks for SRAM voltage stress prediction
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abstract
Static Random Access Memory (SRAM) chips undergo several types of stress in the field, including thermal, electrical, and humidity stress. Existing work has concentrated primarily on humidity and thermal stress; there has been relatively little emphasis on voltage stress level prediction. The objectives of this investigation were to (1) explore the impact of voltage stress on SRAM functionality, (2) observe heating rate differences under voltage stress over time, (3) predict stress levels using artificial neural network models, and (4) develop a generic methodology for voltage stress prediction. A 62256 SRAM CMOS based chip located on an 8051 programming board was studied. Preliminary experiments suggest that as voltage and/or stress time increases, chip temperature increases as well. In addition, the combination of both factors causes the chip to fail within minutes of stress. Artificial neural network models with 3-2-1 and 3-3-1 topologies were constructed to predict stress level given heating rate over time. Thermal profiles of both the entire chip and the die area only were used for neural network model development and evaluation. Results indicate (1) high-voltage stress shortens the lifecycle of SRAM chips, (2) heating rate increases are relatively great in the first few minutes, then reach a steady state, and (3) the neural network model can predict stress level with good accuracy. Using data from the die area yielded the lowest average error rate (3.6 %) and using data from the entire chip yielded a 10% error rate. In addition, the trainRP learning function resulted in a lower error rate than other learning functions such as trainGD and trainCGP.
