publication venue for
- Built-In Self-Test for Multi-Threshold NULL Convention Logic Asynchronous Circuits using Pipeline Stage Parallelism. 38:321-334. 2022
- Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. 31:99-106. 2015
- Pseudo Functional Path Delay Test through Embedded Memories. 31:35-42. 2015
- On-Chip Delay Measurement Based Response Analysis for Timing Characterization. 26:599-619. 2010
- An on-chip spectrum analyzer for analog built-in testing. 21:205-219. 2005
- Verification Simulation Acceleration Using Code-Perturbation. 16:83-90. 2000
- Survey of Robustness Enhancement Techniques for Wireless Systems-on-a-Chip and Study of Temperature as Observable for Process Variations 2011
- Fault Table Computation on GPUs 2010
- Performance-optimized design for parametric reliability 2008